1. Field
The present invention relates generally to delay locked loops and more specifically to delay lines in delay locked loops.
2. Description of the Related Art
Electronic devices, such as, for example, digital signal processors, microcontrollers, memory devices, and other input/output devices often require the use of multiple delayed clock signals. Several techniques have been used to generate multiple delayed clock signals, however, many of these techniques do not meet the timing requirements of high-end electronic devices. For example, multiple rate clock generators (MRCG) may use 32 tap delay lines running at a clock rate of up to 1 GHz, requiring less than 30 picoseconds per tap delay. Standard buffer delay lines or custom cells used in processes using standard voltage threshold transistors often do not satisfy this requirement.
Other multiple rate clock generators often utilize an inverter chain with alternative positive and negative logic to increase clock generation speed. However, the inverter chain may introduce uneven phase shift due to asymmetrical rise/fall propagation delay of the inverter chain in conjunction with alternative logic polarity (alternative NOR and NAND usage).
Therefore, the need exists for an improved electronic system design that generates multiple delayed clock signals.
Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.